The semiconductor industry is rapidly developing chips with smaller and smaller dimensions to gain more functionality per unit area. As the dimensions of devices continue to shrink, so does the gap/space between the devices, increasing the difficulty to physically isolate the devices from one another.
Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned materials on a substrate requires controlled methods for deposition and removal of exposed material.
As the feature size of circuits and semiconductor devices keeps shrinking for higher integration density of electronic components, the self-aligned contact is becoming more and challenging, especially when the critical dimension (CD) of contact holes is smaller than the photolithography limit.
Therefore, there is a need in the art for new methods for self-aligned patterning applications.